Focus on: Advanced Manufacturing     May 16, 2008
IN THIS EDITION...
» How to Detect Non-Overlay Misalignment Errors?
» A Better Way to Manage Test Wafers
» Physical Analysis Provides Images of 45 nm
» Intel, Samsung, TSMC Want 450 mm Wafer Pilot Line in 2012
» SAFC Expands Specialty Chemical Business
» Real Men/Women Do Have Fabs
» Litho Guru Optimistic About Nanoimprint
» Oki Integrates AlGaAs LEDs on Silicon Mounting Chips
» Air Gaps: Unlikely Becoming More Likely?
» ITRS ESH Chapter Emphasizes Sustainable Development
Dear Subscriber,

Manufacturing productivity is always a fascinating subject, and one that spells survival or extinction in the yield-driven semiconductor industry. Managers tackled productivity issues at two recent gatherings: the Advanced Semiconductor Manufacturing Conference (ASMC) in Cambridge, Mass., and SEMI's Strategic Business Conference (Napa Valley, Calif.), both covered by Editor-in-Chief Laura Peters. For her reports and other stories on fab management and semiconductor production technologies, check out our Yield Management Technology Channel:
www.semiconductor.net/yield

David Lammers, NewsEditor
david.lammers@reedbusiness.com

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How to Detect Non-Overlay Misalignment Errors?
Laura Peters, Editor-in-Chief — Semiconductor International, 5/8/2008

Engineers at Semiconductor Manufacturing International Corp. (SMIC, Shanghai) were confronted with an unusual problem in their DRAM fab — how to detect a misalignment error that was not caused by an overlay problem. They worked with Applied Materials to detect this defect using a darkfield inspection tool, which was verified by SEM defect review and FIB cross-section. More

A Better Way to Manage Test Wafers
Laura Peters, Editor-in-Chief — Semiconductor International, 5/8/2008

Advanced Micro Devices (AMD, Sunnyvale, Calif.) is in the process of applying lean concepts throughout its organization — even to highly manual operations, such as the use of test wafers in 300 mm fabs. More

Physical Analysis Provides Images of 45 nm
Laura Peters, Editor-in-Chief — Semiconductor International, 5/6/2008

Engineers at Chipworks Inc. (Ottawa, Canada) have uncovered many physical details of the 65 and 45 nm process technologies. More

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Intel, Samsung, TSMC Want 450 mm Wafer Pilot Line in 2012
Ann Steffora Mutschler, Senior Editor — Electronic News, 5/5/2008

Three industry goliaths — Intel Corp, Samsung Electronics and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) — announced that they have "reached agreement" that the industry needs to start working together to transition to the 450 mm wafer size. More

SAFC Expands Specialty Chemical Business
Laura Peters, Editor-in-Chief — Semiconductor International, 4/30/2008

SAFC Hitech is expanding its business in specialty chemicals for the semiconductor industry. "This cleanroom investment complements existing manufacturing and research and development sites at Sheboygan, and will help us achieve our objectives, essentially providing a 'one-stop shop' for manufacturing, analysis and packaging," said Frank Wicks, SAFC president. More

Real Men/Women Do Have Fabs
Laura Peters, Editor-in-Chief — Semiconductor International, 4/30/2008

Tom Sonderman, vice president of manufacturing technology at Advanced Micro Devices (AMD, Sunnyvale, Calif.), declared at the SEMI Strategic Business Conference (Napa Valley, Calif.) that "real men and women do have fabs." Sonderman described AMD's successes at using feedback to improve their process yields at its fabs in Dresden, Germany. More

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Litho Guru Optimistic About Nanoimprint
Laura Peters, Editor-in-Chief — Semiconductor International, 4/30/2008

Ben Eynon, director of advanced technology development at Samsung (Seoul, South Korea) and associate director of lithography at Sematech (Austin, Texas), discussed Samsung's evaluation of nanoimprint lithography at the SEMI Strategic Business Conference (Napa Valley, Calif.). "The resolution is there for sure, it's a matter of the defects and throughput," he said. More

Oki Integrates AlGaAs LEDs on Silicon Mounting Chips
Kenji Tsuda, Asia Contributing Editor — Semiconductor International, 4/24/2008

Oki Digital Imaging Corp. (Tokyo) is in mass production with LED print heads made with a film bonding technique to integrate AlGaAs epitaxial layers on CMOS silicon ICs. The approach avoids wasting valuable space on bonding pads, resulting in higher-density arrays for LED print heads, Oki managers said at the INC4 conference in Tokyo. More

Air Gaps: Unlikely Becoming More Likely?
Laura Peters, Editor-in-Chief — Semiconductor International, 4/23/2008

The International Interconnect Technology Conference (IITC), held in Burlingame, Calif., June 1-4, will feature papers on the use of air gaps as a low-k dielectric. Air gaps seem to be emerging out of the pure research phase, becoming possible, even likely, to one day be used in production devices. More

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Through-Silicon Vias: Ready for Prime Time?
In this on demand webcast, a panel of experts discuss the various etch, deposition and plating processes required for fabricating TSVs, focusing on unsolved manufacturability challenges. Panelists include: Philip Garrou of Microelectronic Consultants of NC, Jan Vardaman of TechSearch International, and Fred Roozeboom of NXP Semiconductors.
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ITRS ESH Chapter Emphasizes Sustainable Development
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 4/16/2008

Sustainable development is the idea that manufacturing companies can satisfy their present requirements without compromising the needs of future generations. That's a concept that figures prominently in the latest edition of the Environment, Safety and Health chapter of the International Technology Roadmap for Semiconductors (ITRS). More

Aerial Imaging Simplifies Mask Inspection
Alexander E. Braun, Senior Editor, Semiconductor International 4/15/2008

Applied Materials (San Jose) unveiled its new platform, the Aera2 Mask Inspection system, which has been designed to deliver what the company describes as "the fastest, most powerful inspection and qualification solution for all advanced photomasks." Blog

Applied Tackles Edge With Inflexion Polishing System
David Lammers, News Editor, and Laura Peters, Editor-in-Chief — Semiconductor International, 5/7/2008

Applied Materials introduced the Inflexion edge polishing system that has an integrated wafer cleaning capability. The Inflexion tool uses abrasive tape to clean the wafer's edge, an area that faces new contamination issues as immersion lithography pushes liquids to the edge of the wafer. More

 
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