HP Picks Rollable Process for Cheaper Displays
Chris Edwards, Contributing Editor — Semiconductor International, 4/8/2008

Hewlett-Packard has developed a roll-to-roll process for producing polymer electronics displays that the company believes will be much cheaper than conventional processes because of the use of nanoimprint lithography. More

Intel Tackles EUV Mask Cleans
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 4/2/2008

At Sematech's Surface Preparation and Cleaning Conference in Austin, Texas, Intel's Ted Liang detailed the results of a study designed to find solutions for adding zero particle contamination to EUV masks through the cleaning processes. More

EUVA Purchases Further DPSS Lasers for EUV Source Development
Staff — Semiconductor International, 4/9/2008

Japan's EUVA has purchased further DPSS lasers from Powerlase for its work on discharge-produced plasma (DPP) sources for EUV lithography development. More

Obducat Ships Imprint System to Singapore's DSI
Staff — Semiconductor International, 4/8/2008

Obducat AB said Singapore's Data Storage Institute has ordered an imprint lithography system optimized for R&D of patterned magnetic media. Obducat said it will be able to use the installation to deepen ties to the HDD manufacturers based on the island. More

SMEE Shipping Aligner for Back-End Apps
Yao Gang, Editor-in-Chief, SI China — Semiconductor International, 4/7/2008

Shanghai Micro Electronics Equipment Co. Ltd. (SMEE) said its alignment lithography system for wafer-level bump packaging will be used by Chinese packaging companies. SMEE is part of a push by China to develop its domestic machinery and equipment infrastructure. More

Litho a Major Metrology Challenge
Alexander E. Braun, Senior Editor — Semiconductor International, 3/19/2008

Double patterning is among the emerging metrology challenges facing the International Technology Roadmap for Semiconductors (ITRS), said Alain Diebold, a chair of the International Roadmap Committee's Metrology Technology Working Group (TWG). For double patterning to become viable, there must be a considerable improvement in overlay precision. More

Carl Zeiss Opens $30M Advanced Imaging Center
The Business Times Singapore, 3/28/2008

Carl Zeiss officially opened an advanced imaging center in Singapore. The $30M facility allows prospective clients to view and trial the full range of Zeiss micro- and nano-imaging solutions at one location. Previously, they had to travel to several facilities in Germany to test equipment before purchase. More

STMicroelectronics Implements Brion's Tachyon OPC+
Business Wire, 3/27/2008

Brion Technologies announced that STMicro is producing 55 and 45 nm devices using Brion's Tachyon OPC+ optical proximity correction (OPC) solution. More

Etch's Role in Novel Logic Device Patterning
Thorsten Lill, Applied Materials, Santa Clara, Calif.; Steffen Schulze, Mentor Graphics, Wilsonville, Ore. — Semiconductor International, 4/1/2008

The emergence of novel transistor architectures, along with feature size requirements of the 32 nm node, drives the development of new etch technologies. Double patterning, 3-D and high-k metal gates are examples of the latest innovations in the pursuit of the continuation of Moore's Law. More

The Fine Print: 450 mm Wafers: Contamination and Litho Focus
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 4/8/2008

I understand the reluctance to embrace the move to 450 mm wafers from a tool manufacturer's point of view, and probably even more so from a wafer supplier's point of view, but I hadn't thought about the impact that 450 mm wafers would have when it comes to particle contamination and the already shrinking lithography process window. At Sematech's Surface Preparation and Cleaning Conference (SPCC) last week in Austin, I had an interesting conversation with a wet cleans engineer at a major memory manufacturer. The point he made was about how much more important it becomes with a 450 mm plate to avoid backside contamination. Blog

Shadow Lithography for Nanoscale Patterning
Nano World News, 3/23/2008

Shadow Edge Lithography (SEL) has been developed by Jae-Hyun Chung and his group at the University of Washington's Mechanical Engineering Department to offer a low-cost, high-throughput alternative to create features as small as 2 nm on silicon substrates. More

April 16-18, 2008: Photomask Japan

May 12-14, 2008: Sematech Litho Forum

June 10-12, 2008: International Workshop on EUV Lithography