July 23, 2008 | Link This | Email this | Comments (6)

Spanish philosopher and poet, Jorge Santayana’s aphorism that “Those who do not study history are doomed to repeat it,” is widely quoted but generally ignored. I got direct proof of its truth at the recent SEMICON West. While resting my unhappy throbbing feet and downing a double shot of much-needed caffeine, I spoke with the representative of a well-known test company. The conversation eventually drifted from new products to work horror stories, and he told me about the time he asked a client why he still fabricated 70-µm test pads and 120-µm saw streets on his 300-mm wafers. “We’ve always done it that way,” was the reply. Sadly shaking his head in recollection my companion said, “This is the first time I’ve run into ‘legacy’ saw streets and pads. It didn’t matter that...Read More

July 16, 2008 | Link This | Email this | Comments (0)

Although both as journalists and members of the industry we wouldn’t miss coming to SEMICON West, after a couple of days of several very intense meetings with representatives of some of the companies attending, and covering the various events for both the Show Daily (for which we are responsible again this year) and for our Website, it's nice to have the chance to ditch the suit and escape into something pleasant and laid back.

One of these rare escapes is the yearly Semitool (Kalispell, Montana) cruise around the San Francisco ...Read More

July 14, 2008 | Link This | Email this | Comments (2)

Semiconductor manufacturers face tough process and business challenges. On one hand they are required to increase metrology sampling to cope with shrinking process windows, new materials and new architectures, and on the other they are required to reduce cost to maintain profitability. In the case of litho- or etch-based, 32-nm double patterning, for example, there is an increasing need for increased metrology sampling. Shrinking process windows dictate better understanding of metrology uncertainty factors. The 2007 International Technology Roadmap for Semiconductors (ITRS) replaced single term precision, representing variability of a single tool over time, with uncertainty, consisting of three different factors: single tool measurement-to-...Read More

July 13, 2008 | Link This | Email this | Comments (1)

Once more into the breach, dear friends, once more:

Or close up the wall up with our swollen feet…

(With deepest apologies to William Shakespeare.)

Amazingly enough, folks, it’s SEMICON West time again! It seems as if the previous one took place only about three months ago. Of course, after more than 15 years of attending the thing, one’s bound to get a feeling of déjà vu, a sort of Twilight-Zone sensation of a hauntingly recurring event, of racing hamster-like down a M&oum...Read More

July 6, 2008 | Link This | Email this | Comments (0)

As critical dimensions shrink and new materials are introduced, traditional SEMs are running out of steam, making increasingly smaller features more difficult to image, especially as material contrast becomes more challenging. Dedicated ultra-high-resolution SEMs on the market can solve some of these problems, but can be complicated to operate and might have stringent sample preparation requirements. Also, some are optimized for high-resolution imaging at beam currents greater than 10 kV and, when dealing with these kinds of features, lower electron-beam energies are preferable to minimize sample damage, charging, and sample penetration.