Those of you that keep an eye on the Intel Technology Journal have probably seen the write up on their 45 nm Processor Technology. For those that didn’t , I’ll summarize some of the key points here.

The 45 nm process incorporates high-K+metal gate (HiK+MG) transistors for the first time along with third generation strained silicon, nine copper interconnect layers, 193nm dry patterning, and 100% Pb-free packaging. The electrical performance of these products were covered in an IEDM paper last year [ref].

[ref] K. Mistry et al., “A 45nm logic technology with high K+Metal gate transistors, Strained Silicon, 9 Cu Interconnect layers, 193nm dry patterning and 100% Pb-free packaging.&rd...Read More

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Back in February I welcomed the IEEE IITC Conference aboard the 3D Integration bandwagon [ Perspectives From the Leading Edge – 2/26/2008 “IMEC Setting up Shop in Hsinchu”]. After being a bastion of “Low K integration” for the last decade they certainly need to move on. We all recall that the ITRS roadmaps told is in 1998 that the on chip Keff would be 1.6 by 2007. Probably the lesson to be learned here is not to allow your roadmap committees to be overloaded with “pseudo technical” marketing folks from the materials/equipment companies – kind of like letting realtors create your town zoning ordinances ! From a scientific standpoint their bravado never made any technical sense and in the end all things do need to make se...Read More

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Replisaurus Update

Before I update on recent presentations at the Electronic Component Technology Conference (ECTC) I wanted to congratulate Replisaurus [ see Perspectives From the Leading Edge "Electrochemical Pattern Replication or ECPR for short" 1/06/2008 ] on their acquisition of S.E.T. [Smart Equipment Technology, the former device bonder division of SUSS MicroTec] to establish production for its high-volume manufacturing tools for their ElectroChemical Pattern Replication (ECPR™) technology. S.E.T. will be a wholly owned subsidiary of Replisaurus. I’m sure we’ll be hearing more about this exciting...Read More

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I think it was Charles Lassen (who retired from Prismark several years ago and is now sailing the Mediterranean with wife Susan) who once showed me a slide which proved that technology does not become “commercial” until after publications in the area peak and actually begin to decline. The data was irrefutable and held up across a wide variety of microelectronic technologies. With that as a given, I can tell you that 3D Integration “...is not there yet” The May – June time period saw a 3 day focused workshop in Tokyo, several full day sessions at the IEEE / EIA sponsored Electronic Component Technology Conference (ECTC) and a focused session at the IEEE IITC. Over the next few weeks as we head towards Semicon West, I will be highlighting some of the more important / interesting information that was shared at those venues.

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A few weeks back, while on the Suss / STS / NeXX road tour across the US, I felt like I was on one of those tours of Europe that were popular back in the 60’s. You know...the ones where you visit one country per day and after a while the only way you know what day it is, is by the country you are in. By the time Thursday in San Jose rolled around I felt like I was repeating myself....cause I was, only in different cities. As the slides continue to flip you find yourself thinking ...”..didn’t I just cover that one ??”

In San Jose it was great seeing Ed Korczynski in the audience. Ed is Sr technical editor over at Solid State Technology and his blog, over there, is one of my favorites. I like when things are logical....Ed seems to be the same way.

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Picking up where we left off last blog with 3D Integration news from the recent Suss/STS/NeXX road tour I’d like to point out some highlights of the presentations of the two longest lived 3D start-ups Ziptronix and Tezzaron.

Tezzaron

We have discussed the Tezzaron 3D memory technology previously. [ Perspectives From the Leading Edge – “more 3D IC Integration in the AZ desert” April 2008 ] Recall Bob Patti, who already has Chartered fabricating his vias first 3D memory structures, has indicated that (2) other fabs will soon be announcing their adoption of the Tezzaron tech...Read More

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We can all remember the great John Belushi character in Animal House who, when things got a little dull called for a “...ROAD TRIP” Well just as things began to get a little slow on the 3D news front a cross country road trip last week certainly changed all that.

Back in my blog on 08-26-07 “3D Equipment and Materials Vendors Consortium” I informed you that a second equipment/materials consortium was in the process of forming with the same basic goals and functions as EMC-3D. Ends up they would rather not be seen as a “consortium” ( legal implications I assume) so I won’t call them that, but as I’ve said before “…a rose by any other name …you know the rest”. This “loosely affiliated grou...Read More

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It must be nice for those of you living in the Bay area where conferences on every microelectronic topic imaginable are held on an almost weekly basis. Not so for those of us living in the rest of the country. A few weeks ago SMTA held their second 3D, SiP Conference in RTPNC, right here in my back yard. I thought I’d share some of the interesting things that were presented.

Biao Cai of IBM gave a presentation on trends in DRAM packaging for Servers. His key points were:

• Memory capacity growing at minimum 2X per generation
• Memory performance growing at minimum 3X every 3 years
• DRAM technology scaling approaching fundamental limits
• System volumetric space allocation for memory approaching physical limit

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At the recent TSMC “open innovation platform” meeting they described among other things their plans to “…collaborate in the early stages of the IC design process” with their customers. My personal interest lies more in the details they disclosed about their plans for post back end of line activity. According to TSMC's new roadmap, the company is putting more resources into two areas: stacked die packages and 3D.

This announcement should be of concern to the contract assembly and test houses (Amkor, ASE, SPIL, STATS ChipPAC, etc. since such an expansion of services by TSMC will mean a potential loss of business for these assembly houses. While it is unlikely TSMC will produce stacked packages, TSMC has already developed 65-nm wirebond and flip-c...Read More

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By now, if you’re a reader of this blog, you know that I am preaching that 3D IC intregration will happen in an evolutionary not revolutionary fashion (which is how all things have happened in microelectronics over the past 50 years.

We have mentioned several times that 3D process flows have three unit operations in common: (a) TSV formation; (b) thinning and (3) bonding. Since thinning has been optimized in numerous other applications, the infrastructure is currently focused on introducing TSVs and bonding into mainstream production. Bonding technology without TSVs has been introduced by Infineon and Sony and TSVs without bonding are being commercialized by the various image sensor fabricators that we have been discus...Read More

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Finishing up on my coverage of the 3D Integration technology from last months IMAPS Device Packaging Conference in AZ........

NXP Passive Integration Devices to contain TSV

Yannou from NXP (the Philips semiconductor spinout) gave a very nice presentation on their integrated passive technology which they call PICS (passive integration and connecting substrate). We are not talking about Imbedded passives which are passives buried in PWB layers, but rather thin film components similar to what ST Micro has been manufacturing for several years (and they call IPADs).

Their cap...Read More

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This week I’m continuing to share information from the recent IMAPS Device Pkging meeting that was held on the Ft. McDowell reservation north of Scottsdale AZ. Must be because of the time I grew up....but as I type Ft McDowell my mind begins to wander to those great late 1950s westerns .... MGM proudly presents ”Ft McDowell” starring John Wayne, Gabby Hayes and Rita Haywerth. Anyway back to technology......

IMEC

Before I get to presentations and rumors from the meeting I’d like to share with you a new process variation that has been developed by Eric Beyne and the other 3D researchers at IMEC. As you can see from the figure below they first bond th...Read More

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