Overcoming Performance Bottlenecks With Embedded Active Chips

Flip-chip, invented in the early 1960s by IBM (Yorktown Heights, N.Y.), is not a specific package or package type, but rather a method of electrically connecting the die to a carrier (substrate or leadframe). The carrier acts as an interposer between the die and external system (typically a PCB). In standard packages, the die is attached face-up (active circuitry facing up) on the carrier and a wire is used as a connection between the peripheral pads on the die and carrier. The wires are typically 1–5 mm in length and 0.8 to 1.3 mil in diameter. With applications demanding multi-gigahertz speed and instantaneous currents from the power supply, the high impedance behavior and loss characteristics of wire bonds can limit the overall system performance. In contrast, in flip-chip, the die is assembled facedown on the carrier. The pads in a flip-chip application connect to the carrier using conductive bumps that are typically only 70–100 μm high and 100–125 μm in diameter.

Flip-chip ball grid array package

A generic, low-pin-count flip-chip ball grid array (FCBGA) package uses a laminate-based substrate as a carrier, and the overall construction is similar to that of a carrier using a wire bond chip. The substrate is generally two to six layers of alternating metal and dielectric layers. Mechanically drilled through-hole vias are used to connect to different layers of the substrate. Through-hole vias occupy valuable routing space on the carrier, and this carrier type is only limited to low-pin-count applications.

In applications demanding greater functionality with higher pin counts, the substrate consists of a combination of core and built-up dielectric and metal layers (6–14 metal layers). A typical substrate manufacturing begins with a two- or four-layer copper clad core, followed by etching the copper layers to get the required electrical pattern. A series of built-up dielectric and metal layers are then added onto this typically thick core. A flip-chip die is connected on one side of this carrier, and solder balls form the connection between the carrier and PCB on the other side. To improve routing efficiency, blind and buried vias are used rather than through-hole vias. The vias through the core are mechanically drilled, and vias through the built-up layers are created using laser drilling techniques. Figure 1 shows a cross-section of a typical high-performance FCBGA package.

1. Cross-section of a typical FCBGA package showing the vertical interconnect transition from solder bumps at the chip to solder balls.

FCBGAs offer many advantages, including:

• Increased functionality in a smaller die — The entire surface area of the die is available for die bump placement to connect to a carrier, which eliminates the wire bond restriction of having all of the pads at the periphery of the chip.
• Improved power supply noise performance — Significantly lower loop inductance because of an order of magnitude reduction in die-to-carrier interconnect length. Also, power can be supplied right where it is going to be used instead of being routed toward the edge of the die and then brought in toward the core or I/O circuitry in wire bond packages.
• Superior signal integrity performance — The high impedance nature of the wire bonds creates impedance discontinuities in fast-switching environments, degrading the signal integrity performance. Wire bonds also suffer from considerably larger signal-to-signal crosstalk. These phenomenon are significantly mitigated in flip-chip interconnects with controlled impedance lines and smaller signal-to-signal crosstalk.
• Reduced package footprint — Potential reduction in package size because FCBGA packages do not require a keep-out area for connecting to the carrier as in wire bond packages.

Each signal and power supply connection from the chip to the PCB has a large core via in its interconnect path. The core via is mechanically drilled to connect the top and bottom layers of a typical two-layer core. The core thickness can range from 400 to 800 μm. Although numerous advantages exist in a FCBGA package, its electrical performance can be further improved by removing this core via from the interconnect path. Embedding the chip in the core of the substrate removes the large core via from the interconnect path and helps bring the chip electrically closer to the PCB. This technology is discussed in greater detail in the following sections.

Embedded active chip technology

Instead of the chip mounted on the top side of the substrate, the chip is embedded in the core of the substrate with the dielectric and metal layers built up on one side of the core (Fig. 2). This one-sided built-up process brings the terminals on the chip almost to the circuit-board level and is conceptually closest to directly attaching the chip to the PCB. The large core vias present in the interconnect path for each signal and power supply connection are eliminated with subsequent gains in electrical performance. The overall thickness of the package is reduced by at least 400–800 μm, making it desirable in applications demanding a lower Z direction profile.

2. Embedding the chip in the core of the substrate removes the large core via interconnect, shortening the chip to PCB distance.

Manufacturing processes for this technology are consistent with a regular high-performance flip-chip package, except for some modifications. A cavity ~50 μm bigger than the flip-chip is created in the dielectric core. The chip and core dielectric are then attached to a copper stiffener. The stiffener serves a dual purpose of providing mechanical stability to the overall package and offering superior thermal performance. A dielectric layer is built up on the exposed side of the chip. Vias are drilled using a laser drilling technique to connect to the chip pads, so that the solder bumping step is eliminated compared with the traditional approach. The desired conductor pattern is added on the dielectric layer using an electroless copper plating technique. This step of alternating conductor and dielectric layers is repeated until all required connections are complete.

Performance improvement

Relative to the FCBGA, the embedded active chip package offers improvements in signal integrity, power supply noise and thermal performance.

Signal integrity (crosstalk) performance — Crosstalk noise from an aggressor pin to a victim pin in a BGA package is predominantly inductive in nature and caused by the overlap of the victim signal-return loop and aggressor signal-return loop. A larger loop-area overlap will cause an increase in crosstalk noise. Because of the large core via, the signal-return loop area of the FCBGA package is significantly larger than that of an embedded active chip package. Figure 3 shows the near-end crosstalk (NEXT) and far-end crosstalk (FEXT) vs. frequency performance comparing the two package types. The data shows ~4–5 dB improvement for the embedded option vs. the FCBGA option.

3. Crosstalk performance is improved for the embedded active chip technology vs. the typical FCBGA package at different frequencies caused by smaller signal-return loop overlaps.

Figure 4 shows the time-domain quiet-mode crosstalk performance for the victim net when aggressor on either side switches 0 to 1 V with 250 picoseconds rise and fall times. The noise waveforms show ~35–40% improvement in crosstalk performance for the embedded active chip package compared with the FCBGA package.

4. The time domain near-end (NEXT) and far-end (FEXT) crosstalk waveforms for the two packages. This is a sample scenario of improvement in crosstalk performance when the aggressor signals are on either side switch.

Power supply noise performance — Voltage noise across the chip power and ground is proportional to the impedance of the power supply loop through the package. Impedance is a function of the loop inductance of the package power and ground connections and increases with a larger loop area. The power supply loop is an order of magnitude larger in the FCBGA package because of the core vias resulting in higher input impedance compared with the embedded chip package. Figure 5 shows a simplified view of one power and ground connection from the top of the carrier substrate to the bottom for the FCBGA package with details on the overall Z direction distance. With the absence of the core via, the loop area is significantly smaller in the embedded chip package.

5. An example power supply loop through a FCBGA package.

Thermal performance — The majority of the heat generated at the chip junction in both package options escapes through the case and solder balls. In both FCBGA and embedded chip packages, the backside of the chip is attached to a copper heat spreader with a comparable junction-to-case thermal resistance performance (<1 C/W). Thermal resistance offered to the flow of heat through the solder balls is at least three times smaller for the embedded active chip package compared with the regular FCBGA package because of the longer and more resistive heat flow path through the thick core in the FCBGA package, improving the overall thermal performance of this technology.

Some of the salient features of this technology include:

• The solder bumping process is eliminated. The dielectric layer is built up directly on the chip and laser vias are drilled through the dielectric to connect to the chip pads.
• It provides superior signal and power integrity performance.
• It improves thermal performance compared with the regular FCBGA package.
• This technology offers potential reduction in package footprint because of the elimination of core vias, reducing the area of the fan out from the chip to connect to the solder balls and, hence, allowing true chip-scale packaging with increased integration levels.
• It provides significantly smaller Z direction profile.
• It is presently limited to four layers in production.

On a side note, to convert an existing wire bond chip to an embedded active chip, a redistribution layer (RDL) is required to change the location of the peripheral die pads in the wire bond die to an area array-type distribution for the embedded option. The minimum bump pitch allowed in the embedded option is 200 μm. If the die pad pitch for the wire bond chip was >200 μm, then an RDL layer is not necessarily required. But, in most applications, the die pad pitch is <100 μm. Figure 6 shows an example RDL layer used to convert the peripheral pads to an area array pattern for a wire bond chip.

6. A sample RDL layout for converting an existing wire bond die with peripheral pads to an area array pattern.