Advanced Metallization Needs Integrate Copper Into Memory

Copper has displaced aluminum to become the standard back-end-of-line (BEOL) metallization material for advanced logic devices. However, integrating copper interconnects in memory devices is not a simple technology transfer from logic. Memory devices present unique challenges to be solved before copper's benefits can be realized.

Flash and DRAM interconnects have distinct requirements, so logic processes cannot be directly transferred. (Source: Applied Materials)

Copper integration challenges

In logic devices, copper is used in all BEOL metallization after the tungsten contact; in DRAM and flash, it is being integrated only in select areas. In DRAMs, copper is only introduced after formation of the stacked capacitors. The bitline metallization formed before stacked capacitors will remain tungsten because of thermal budget constraints (Fig. 1). Even at BEOL, all metal layers may not be converted to copper. The last metallization layer may remain aluminum for simpler bond pad integration. In flash memory, copper metallization is being introduced at the bitline level. Figure 1 shows representative diagrams of typical flash and DRAM structures with copper metallization.

1. Cross-sectional diagrams of DRAM and flash structures showing potential copper integration (orange lines) with aluminum on the final metal level for bond pad.

This hybrid copper and aluminum (or tungsten) scheme poses significant integration challenges. Robust Cu-Al or Cu-W barriers are required to prevent aluminum diffusion into the copper (dominant mechanism) or tungsten hexafluoride (WF₆) penetration into the underlying copper. The fluorine's source is entrainment from the deposition process. Because DRAM and flash are price-sensitive commodities, alternate barrier materials to those used in logic must be considered to reduce material cost without compromising reliability and fab productivity.

The Cu-W scheme seems likely to be adopted by the majority of DRAM and flash manufacturers because of experience with logic's tungsten contacts and its lower integration complexity compared with the Cu-Al scheme. The leading candidate for the barrier diffusion scheme is currently being evaluated.

In DRAM, the M0 bitline is currently tungsten and the M1 (and/or M2) is transitioning from aluminum to copper. This layer has very relaxed linewidth and aspect-ratio (AR) requirements (Table). Furthermore, electromigration (EM) for DRAM may not be an issue because of relatively low current density and low operating temperatures. Thus, DRAM reliability specifications may be more readily achieved than for flash.

In flash memory, as the M0 (and/or M1) bitline is converted to copper at the ≤5X/4X technology nodes, the biggest challenge is to achieve complete gap fill in small trenches. Flash has aggressive trench CD specifications for copper barrier/seed and electrochemical plating (ECP) fill. Typical geometries at 3X are expected to be 35 nm, 4:1 AR, which will require innovation in physical vapor deposition (PVD) copper deposition technology to meet these requirements. Also, flash operates at higher voltage levels and has stringent dielectric breakdown voltage (V_bd) and time-dependent dielectric breakdown (TDDB) requirements. This requires barrier film optimization to improve device electrical property and alternate barrier materials for production efficiency.

Barrier film optimization

As trench linewidths are scaled, the high voltage used in flash compared with logic, makes meeting the V_bd and 10-year TDDB specifications challenging for the copper barrier process.

To test the compliance of a device against TDDB requirements, the device is stressed at various electric field strengths to measure breakdown time (T_bd) and voltage. A line fitted to the test data is extrapolated back to the 10-year specification of 0.5 MV/cm. The device under test (DUT) in this example has met the requirement (i.e., it will have a projected >10-year T63 lifetime).

Another requirement is to engineer barrier film property for conformal coverage inside small features to provide a conductive wetting layer for copper seed and prevent copper migration in the dielectric material. Innovation in PVD Ta(N) source technology has enabled the capability to deposit conformal barrier with minimal overhang inside ≤50 nm trench/via features (Fig. 2). The enhanced barrier properties widen copper gap fill and improve device electrical results.

2. Innovative PVD Ta(N) source forms conformal coverage inside aggressive feature.

Further barrier film optimization knobs have been studied to address premature failures caused either by the bulk dielectric film's properties or by breakdown of the interface between the dielectric and an adjacent film. During chemical mechanical planarization (CMP), poor barrier adhesion can cause delamination from the dielectric sidewall and redeposition between metal lines. The redeposited material forms a bridge between adjacent lines, causing failure at very low test voltages. Furthermore, high stress barrier films can cause V_bd issues also because of poor barrier adhesion to the underlying dielectric layer. Barrier adhesion optimization to the dielectric is basic for good V_bd performance.

Modifying the barrier layer material can reduce film stress and improve barrier adhesion. Introducing N₂ gas into the tantalum barrier deposition process results in TaN barrier film; TaN adhesion data shows higher adhesion strength to dielectric (~12 J/m²) compared with tantalum (~6 J/m²).¹ Thus, a TaN underlayer is believed to minimize barrier delamination risks. TaN films have superior V_bd characteristics than tantalum alone, but otherwise have similar electrical properties (i.e., the modified barrier layer does not negate copper's resistivity benefits).

Another way to reduce barrier film stress and improve dielectric adhesion is to decrease the deposition energy. The low-energy TaN process achieves a 25% reduction in compressive stress from 4 TPa to 3 TPa. Through a process similar to peening, high-energy deposition may result in dielectric surface damage, contributing to higher film stress and degradation of interface adhesion properties.

To investigate the effect of various deposition energy on V_bd, 130 nm pitch (350 Å SiN/1300 Å undoped silica glass with 300 Å etch in undoped silica glass) test structures were prepared with different space/width (45/85 nm, 30/100 nm, 65/65 nm). The structures fabricated with the low-energy TaN process had ~8% higher V_bd compared with the high-energy deposition process, perhaps because of minimal dielectric surface modification and resulting stronger interface. Additional experiments showed an increase in V_bd (~15%) with a thinner barrier layer and cleaner surfaces between metal lines featuring reduced redeposited residue after CMP.

To lower material cost and improve performance, titanium is being considered as an alternative barrier metal. It has ~4× lower cost ($/wafer) when compared with the tantalum baseline. It has been noted that TiO_x, formed by a reaction with atmospheric oxygen, has a lower molecular volume expansion ratio than tantalum.² This helps avoid crack formation in the barrier layer caused by thermal cycling. These cracks can allow atmospheric oxygen to reach the underlying copper and form higher-resistivity CuO. TiO_x also forms a higher-conductivity barrier layer compared with TaO_x. These properties suggest titanium could be a superior adhesion layer to copper. Titanium is also more resistant to moisture outgassing from the dielectric material, which can also result in the formation of CuO. Titanium has been shown to consistently improve downstream EM performance while showing similar stress migration (SM) compared with the tantalum baseline (Fig. 3).² Superior reliability performance with titanium has made it a suitable alternative barrier metal for logic interconnects.² Breakdown voltage tests were carried out, demonstrating that titanium had a V_bd similar to tantalum, making it a suitable candidate for memory interconnect application.

3. The titanium barrier demonstrates significant improvement in EM and similar SM performance to tantalum. Data from MTCG test structures.

In addition to good reliability, titanium must demonstrate good gap-fill extendibility to 3X/2X trench sizes for flash. We have shown good step coverage and gap fill on 3X node trenches using a PVD process (Fig. 3).

Copper seed extendibility

As feature sizes shrink, the PVD copper seed layer must be made thinner to minimize overhang. This may result in discontinuous coverage and incomplete ECP gap fill. This problem is more severe at the wafer edge, where off-angle copper deposition causes sidewall coverage asymmetry. This phenomenon narrows the gap-fill process window and causes end-of-line voids and post-CMP defects that reduce yield.

At the 4X and 3X nodes, robust barrier and seed systems and processes have been developed that demonstrate good gap-fill performance. The problem of sidewall coverage asymmetry during deposition caused by line-of-sight, or off-axis, effects was addressed by moving the magnetron in a profile motion during deposition. Cu⁺ ions reach each sidewall with the same distribution of incidence angles regardless of where the features are located on the wafer; sidewall coverage in the seed process was improved by the addition of a second plasma source. RF coils are placed around the periphery of the reactor, thus, the reactor has two independently controlled plasma sources to introduce Cu⁺ flux during deposition and pure argon etch to improve side coverage by resputtering. The resputtering step, performed after deposition, uses argon plasma to redistribute deposited copper within the trench to achieve more uniform coverage of sidewall and trench bottom areas.

These reactor modifications led to improvements in the subsequent copper gap fill. In the case of 4X node features, a complete fill was possible for dramatically thinner seed layers, demonstrating improved seed layer uniformity across the substrate.

4. New copper reactor modifies fundamental properties of ionized species and significantly improves copper seed step coverage and subsequent fill.

Recent breakthroughs in PVD copper source technology will likely extend PVD to the 2X node. Simultaneously, atomic layer deposition (ALD)/chemical vapor deposition (CVD) technologies are pursued to extend copper barrier/seed metallization to 1X node and below. ALD/CVD has been explored since 90/65 nm node development, but implementation was delayed because of innovation in PVD source technologies. Recently, ALD has been implemented in volume production at a logic manufacturer for critical metallization applications. The same ALD hardware is leveraged to deposit a thin (~2 nm) conformal seed enhancement layer between thin PVD barrier/seed layers to create a wider trench/via opening and more room for ECP gap fill (Fig. 5).

Two seed enhancement materials under development are ruthenium deposited by PVD or ALD and cobalt deposited by CVD. Good gap fill and device parametric/reliability (SM/EM) has been demonstrated with PVD ruthenium, ALD ruthenium and CVD cobalt seed enhancement processes. Gap-fill verification using this approach has been demonstrated on 50 nm via test structures with 5:1 AR (Fig. 5). Without an enhancement layer, insufficient seed causes voids; with it, consistent gap fill is achieved. The hurdles with these approaches are cost and ECP/CMP integration. PVD/CVD ruthenium is expected to be more expensive and requires optimization of the CMP process. On the other hand, CVD cobalt has a similar CMP polish rate to tantalum and is attractive from the cost perspective, but tends to dissolve in the ECP bath. By changing the ECP process, cobalt dissolution can be significantly inhibited, enabling gap-fill extendibility.

5. Introducing a seed enhancement layer allows significantly thinner barrier/seed stack gap-fill extendibility demonstrated on 50 nm, 5:AR vias.

The addition of the enhancement layer does not significantly enhance process flow complexity. Cluster-type deposition systems are available with sufficient flexibility to mix PVD and CVD reactors, allowing integrated processing without exposing the substrate to ambient atmospheric moisture and other contamination sources.

Cu/W or Cu/Al diffusion barrier

A new integration challenge with copper in memory is the integration with subsequent tungsten or aluminum steps. In addition to an ideal barrier requiring blocking properties for copper and fluorine in case of Cu-Al, Cu-W scheme, the barrier must have good step coverage, reasonable low resistance and survive thermal treatments.

Barrier failure with tungsten contact appears as voiding in the underlying copper because of its reaction with fluorine, sometimes with copper within the tungsten plug. The failure mechanism included a weak barrier, incomplete barrier coverage (made more challenging by the occasional etch undercut at the feature bottom) or damaged barrier — this leads to the need for a conformal and dense barrier. Barrier fracture can occur because of copper extrusion if there is inadequate thermal control with the subsequent tungsten processes.

Several barrier combinations have been evaluated, including PVD Ti/TiN and bilayer barriers with PVD tantalum or titanium and metal-organic chemical vapor deposition (MOCVD) TiN. Our experience shows that a bilayer PVD/CVD barrier offers the best performance. Advanced PVD tantalum or titanium with excellent step coverage created a dense copper barrier on the feature bottom. This was followed in situ by a highly conformal MOCVD TiN plasma treated to achieve high density yet remain amorphous, which performed as a good fluorine barrier for CVD tungsten fill. Additional PVD Ti/TiN tests show that oxidation of TiN instead of titanium and optimizing Ti/TiN thickness is important for good barrier properties.

In the case of Cu-Al, barrier failure occurs with both copper and aluminum diffusion through the barrier, forming a high resistance TiCu phase and the creation of voids.

We investigated several barrier combinations, including PVD Ti/TiN, Ta/TaN, and PVD CVD bilayers with PVD tantalum or titanium and MOCVD TiN. We also considered the use of O₂ and silicon stuffing to enhance barrier properties. In general, barrier performance is improved with O₂ stuffing; however, there is a trade-off in increased via resistance that requires careful optimization of the PVD (and CVD) deposition processes. Tantalum is superior to titanium, but costlier. PVD can meet most requirements, but for the more aggressive structures, PVD/CVD bilayer barriers perform best. Sometimes, for wider via structures, the Cu-Al barrier process may be executed within existing M2 aluminum fill systems, enabling the extension to copper in memory within minimal incremental capital expenditure.

Conclusions

Historically, logic interconnect technology has been driven by dual damascene feature scaling, low-k integration and copper interconnect reliability (EM/SM) performance requirements. With memory devices transitioning from aluminum to copper, requirements such as gap-fill extendibility are more challenging. Near-term, memory is unlikely to adopt low-k, but high-voltage device operation and aggressive trench spacing and width scaling present new challenges to meet line-to-line leakage and V_bd requirements. Additionally, because most memory makers continue to use an aluminum bond pad as the top metal layer, there is a new requirement to develop robust Cu-Al or Cu-W diffusion barriers. Alternative barrier materials, such as titanium, may be introduced.