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The latest news and information on semiconductor yield management, including process control, reliability, defect detection and design for manufacturing.

  • Yield Goals for 22 nm
    Dilip Patel, Kye-Weon Kim, Doron Arazi, John Allgair, Benjamin Bunday, Milton Godwin, Victor Vartanian, Pete Lipscomb and Aaron Cordes, International Sematech Manufacturing Initiative (ISMI), Austin, Texas - 06/01/2008
     The industry is on target to deliver necessary defect metrology and film metrology solutions, but new overlay target structures are needed for 22 nm monitoring. More

  • ATE Industry Maneuvers Around ‘Perfect Storm’ of Issues at 90 nm and Below
    Sally Cole Johnson, Contributing Editor - 06/12/2008
     The combination of discrete challenges, design sensitivity and integration issues are creating complex challenges for ATE vendors. More
  • Electromigration-Induced Failures in Plastic Encapsulated IC Packages
    William Eslinger, Boston Scientific, St. Paul, Minn. - 06/01/2008
     IC failure analysis performed on potentiometer ICs revealed intermittent electrical shorts caused by a metal stringer problem. More
  • Yield, Surface Prep for Nano Devices
    Ahmed Busnaina, William Lincoln Smith Professor and Director, The NSF Nanoscale Science and Engineering Center for High-rate Nanomanufacturing and the NSF Center for Microcontamination Control - 06/01/2008
     Nanoscale emerging research devices in the "beyond CMOS scaling" realm cover many applications and state variables. There have been many discussions of the characteristics, performance requirements, etc., of these devices, but the manufacture of these devices and the resulting yield has not been addressed. More
  • How to Detect Non-Overlay Misalignment Errors?
    Laura Peters, Editor-in-Chief - 05/08/2008
     Engineers at SMIC were confronted with an unusual problem in their DRAM fab — how to detect a misalignment error that was not caused by an overlay problem. They worked with Applied Materials to detect this defect using a darkfield inspection tool, which was verified by SEM defect review and FIB cross-section. More
  • A Better Way to Manage Test Wafers
    Laura Peters, Editor-in-Chief - 05/08/2008
     Advanced Micro Devices is in the process of applying lean concepts throughout its organization — even to highly manual operations, such as the use of test wafers in 300 mm fabs. More
  • Applied Tackles Edge With Inflexion Polishing System
    David Lammers, News Editor, and Laura Peters, Editor-in-Chief - 05/07/2008
     Applied Materials introduced the Inflexion edge polishing system that has an integrated wafer cleaning capability. The Inflexion tool uses abrasive tape to clean the wafer’s edge, an area that faces new contamination issues as immersion lithography pushes liquids to the edge of the wafer. More
  • Real Men/Women Do Have Fabs
    Laura Peters, Editor-in-Chief - 04/30/2008
     Tom Sonderman, vice president of manufacturing technology at Advanced Micro Devices (AMD, Sunnyvale, Calif.), declared at yesterday’s SEMI Strategic Business Conference (Napa Valley, Calif.) that “real men and women do have fabs.” More
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Alexander E. Braun
The Measure of All Things
Alexander E. Braun, Senior Editor, Semiconductor International
July 14, 2008
Standalone Pushes Optical CD Boundaries
Semiconductor manufacturers face tough process and business challenges. On one hand t...
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Alexander E. Braun
The Measure of All Things
Alexander E. Braun, Senior Editor, Semiconductor International
July 6, 2008
SEM Enables Rapid Subnanometer 3-D Surface Imaging
As critical dimensions shrink and new materials are introduced, traditional SEMs are ...
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Alexander E. Braun
The Measure of All Things
Alexander E. Braun, Senior Editor, Semiconductor International
May 9, 2008
Revisiting a Conference and Some Ongoing Problems
During a conversation on some of the lithography and metrology technology problems th...
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Alexander E. Braun
The Measure of All Things
Alexander E. Braun, Senior Editor, Semiconductor International
April 15, 2008
Aerial Imaging Simplifies Mask Inspection
Mask inspection certainly has not been made any easier by the continuing complexity b...
More

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Vivek Bakshi, EUV Litho Inc.
Advocating More Open Communication on EUV Lithography

Vivek Bakshi, founder and president of EUV Litho Inc., explains why he started up the International Workshop on EUV Lithography, which took place in Maui in June. He also expands on recent developments in EUV, and why more research is needed.

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CMOS and Beyond: Surface Prep at Nanoscales
Now Playing: CMOS and Beyond: Surface Prep at Nanoscales
At SEMICON West 2006, Alex Braun interviews Ahmed Busnaina, director of the NSF Nanoscale Science and Engineering Center for High-Rate Nanomanufacturing at Northeastern University. Busnaina gives his perspective on the longevity of CMOS, nanotechnology, and surface preparation at nanoscales.
Video Table of Contents  More Videos >>





Technical Articles

    Yield Goals for 22 nm
Dilip Patel, Kye-Weon Kim, Doron Arazi, John Allgair, Benjamin Bunday, Milton Godwin, Victor Vartanian, Pete Lipscomb and Aaron Cordes, International Sematech Manufacturing Initiative (ISMI), Austin, Texas, 06/01/2008
 The industry is on target to deliver necessary defect metrology and film metrology solutions, but new overlay target structures are needed for 22 nm monitoring....

    Electromigration-Induced Failures in Plastic Encapsulated IC Packages
William Eslinger, Boston Scientific, St. Paul, Minn., 06/01/2008
 IC failure analysis performed on potentiometer ICs revealed intermittent electrical shorts caused by a metal stringer problem....

    Yield, Surface Prep for Nano Devices
Ahmed Busnaina, William Lincoln Smith Professor and Director, The NSF Nanoscale Science and Engineering Center for High-rate Nanomanufacturing and the NSF Center for Microcontamination Control, 06/01/2008
 Nanoscale emerging research devices in the "beyond CMOS scaling" realm cover many applications and state variables. There have been many discussions of the characteristics, performance requirements, etc., of these devices, but the manufacture of these devices and the resulting yield has not been addressed....

More View all stories


EVENTS

ESD/Latchup Design and Technology
Aug. 3-4, 2008
Tel Aviv, Israel
Failure and Yield Analysis
Aug. 5-7, 2008
Tel Aviv, Israel
EOS/ESD Symposium
Sept. 7-12, 2008
Tucson, Ariz.

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