The latest news and information on major semiconductor manufacturing process steps, including etch, deposition, epitaxy, chemical mechanical planarization (CMP) and thermal processing.
TSV Apps Need TSV Tools Laura Peters, Editor-in-Chief - 07/01/2008
While key applications in CMOS image sensors and stacked memories continue to drive 3-D technology, a significant need from the tool side is still unmet: production-worthy throughputs. More
Memory Moves to Megafabs for NAND David Lammers, News Editor - 07/17/2008
At SEMICON West, companies were discussing wafer processing tools, automation equipment and other pieces of the chip manufacturing infrastructure. The target: big memory megafabs.
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Roadmap Signals Showstoppers Laura Peters, Editor-in-Chief - 07/17/2008
The overall theme of the 2008 update to the International Technology Roadmap for Semiconductors (ITRS) is a slight slowdown of gate-length scaling for high-performance and low-standby power devices, but the low-power device target dates will not change.
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OEM Group Buys ‘Legends’ Tools From Applied David Lammers, News Editor - 07/16/2008
The OEM Group has acquired the “Legacy” tools from Applied Materials, bringing the Eclipse PVD system and AGHeatpulse RTP tool into its fold. Applied had acquired the tools as part of its 2004 Metron Technology Inc. acquisition.
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When Will 450 mm Make Economic Sense? Jonathan Davis, Executive Vice President, Global Expositions, Marketing, Communications and EHS, SEMI, San Jose - 07/15/2008
There is an industry-wide curiosity about the reality behind a wafer size transition to 450 mm. According to the International Technology Roadmap for Semiconductors (ITRS), this transition should happen in 2012 to keep the industry on Moore’s Law, and a few companies are pushing hard to make this happen.
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Novellus Debuts Deposition Tools During West David Lammers, News Editor - 07/15/2008
Novellus Systems (San Jose) unveiled two tools at the Yerba Buena Center of Arts during SEMICON West. The Vector Extreme AHM is aimed at the growing use of ashable hard masks (AHMs) by the large memory chip vendors. A high-density plasma CVD tool, Speed Max, targets the gap-fill sector.
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Intermolecular Speeds R&D for Elpida’s Next-Gen Memory Aaron Hand, Executive Editor, Electronic Media - 07/15/2008
Intermolecular Inc. (San Jose) today announced a new collaborative development program (CDP) and licensing agreement with Elpida Memory Inc. (Tokyo) to enable rapid development of new materials and process technologies for Elpida’s next-generation memory chips.
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Etcher Tuned for Double Patterning, Advanced Gates Laura Peters, Editor-in-Chief - 07/13/2008
Lam introduced the Versys Kiyo3x Conductor etch platform, the capabilities of which can be applied as an upgrade to existing Versys Kiyo etchers, largely to address uniformity considerations of advanced gate and double patterning for 3X logic and flash chipmakers and 4X-5X DRAM makers.
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Views on News David Lammers, News Editor, Semiconductor International June 27, 2008 IBM@45: eDRAM, Si! High-k, No
It now appears that IBM Corp. plans to implement a high-bandwidth silicon-on-insulato... More
Float Zone Laura Peters, Editor-in-Chief, Semiconductor International June 16, 2008 What's With the Name?
Welcome to the debut of my very own blog, the Float Zone. Float zone wafers first cam... More
Vivek Bakshi, founder and president of EUV Litho Inc., explains why he started up the International Workshop on EUV Lithography, which took place in Maui in June. He also expands on recent developments in EUV, and why more research is needed.
Now Playing: CMOS and Beyond: Surface Prep at Nanoscales At SEMICON West 2006, Alex Braun interviews Ahmed Busnaina, director of the NSF Nanoscale Science and Engineering Center for High-Rate Nanomanufacturing at Northeastern University. Busnaina gives his perspective on the longevity of CMOS, nanotechnology, and surface preparation at nanoscales. More Videos >>
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Technical Articles
Self-Aligned Barrier Improves Interconnect Reliability H.J. Wu, J. O'loughlin, R. Shaviv, M. Sriram, K. Chattopadhyay, Y. Yu, T. Mountsier, B. van Schravendijk, S. Varadarajan, G. Dixit and R. Havemann, Novellus Systems Inc., San Jose, 05/01/2008
A new PECVD self-aligned barrier using a germanium dopant offers a simple, cost-effective means of improving electromigration resistance of copper interconnects....
Advanced Metallization Needs Integrate Copper Into Memory Niranjan Kumar, Kevin Moraes, Murali Narasimhan and Prabu Gopalraja, Applied Materials Inc., Santa Clara, Calif., 05/01/2008
Logic interconnect technology has been driven by dual-damascene feature scaling, low-k integration and copper interconnect reliability performance requirements. With memory devices going from aluminum to copper, requirements such as gap-fill extendibility are more challenging....
Improving Electrical Performance Using SACVD Oxide Films Cary Ching, Harry Whitesell and Shankar Venkataraman, Applied Materials Inc., Santa Clara, Calif., 04/01/2008
An O3/TEOS-based sub-atmospheric CVD process demonstrates improved drive current, junction leakage and superior gap fill for aspect ratios >8:1 for STI and >6:1 for PMD. Use in a locally strained channel device is also demonstrated....
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Sept. 9-11, 2008
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Dec. 3-5, 2008
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