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The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation.

  • Release Film Boosts IC Molding Productivity
    Kenji Tsuda, Asia Contributing Editor - 07/23/2008
     Asahi Glass has developed a release film for molding thin ball grid arrays (BGAs) or chip-scale packages (CSPs). The company said the film reduces resin usage, and nearly eliminates the frequent mold cleanings required with conventional molding technologies. More

  • Molding Techniques Support Thin Gold Wires, Low-k Materials
    Kenji Tsuda, Asia Contributing Editor - 07/21/2008
     Competing Japan-based molding machine manufacturers have developed techniques that support the thinner packages required for cell phones. The new molding methods also ease the mechanical pressure placed on the relatively fragile low-k dielectric materials in leading-edge logic devices. More
  • The Mobile Life: Carry Small, Live Large
    Alexander E. Braun, Senior Editor - 07/17/2008
     In his keynote address, “The Mobile Renaissance: The Era of Smarter SoCs,” Gadi Singer, vice president of the Mobility Group and general manager of the SoC Enabling Group at Intel (Santa Clara, Calif.), shared his compelling vision on the future of the mobile industry. More
  • Roadmap Signals Showstoppers
    Laura Peters, Editor-in-Chief - 07/17/2008
     The overall theme of the 2008 update to the International Technology Roadmap for Semiconductors (ITRS) is a slight slowdown of gate-length scaling for high-performance and low-standby power devices, but the low-power device target dates will not change. More
  • High-Density Packaging Possibilities
    Karl Stuber, Senior Director, Test, Assembly and Packaging, SEMI, San Jose - 07/15/2008
     A recent analysis of a high-end cell phone found 65 active single and multi-chip packages (MCPs) with I/Os ranging from 2 to 447 pins, with the large majority having <200 I/Os. Mobile device manufacturers today are incorporating more than 30 wafer-level chip-scale packages (WLCSPs) into their high-end cell phones. More
  • Wire Bond Tester Targets Zero Field Failures
    Laura Peters, Editor-in-Chief - 07/15/2008
     It may soon be possible to non-destructively test wire bond quality in real time during automated wire bonding and “bin” the failures, as is possible in electrical test. More
  • New Packaging Technologies Dominate Best of West Awards
    Thomas Morrow, Vice President of Global Expositions and Marketing, SEMI, San Jose - 07/11/2008
     Underscoring the degree of innovation occurring in semiconductor packaging, four of the eight finalists in the Best of West awards were new packaging technologies — three of these serve in 3-D IC applications. More
  • Why 3-D TSV is Hotter Than Hot
    E. Jan Vardaman, President, TechSearch International Inc., Austin, Texas - 07/11/2008
     The adoption of 3-D TSV technology promises higher clock rates, lower power dissipation, and higher integration density. More
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Philip Garrou
PERSPECTIVES FROM THE LEADING EDGE
Philip Garrou, Consultant,
July 16, 2008
Intel 45 nm Processor Technology for Mobile Products
Those of you that keep an eye on the Intel Technology Journal have probably seen the ...
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Philip Garrou
Perspectives From the Leading Edge
Philip Garrou, Consultant,
July 7, 2008
IITC on the 3D Integration Bandwagon
Back in February I welcomed the IEEE IITC Conference aboard the 3D Integration bandwa...
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Philip Garrou
Perspectives From the Leading Edge
Philip Garrou, Consultant,
June 28, 2008
More 3D Integration at ECTC 2008
Replisaurus Update Before I update on recent presentations at the El...
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Philip Garrou
Perspectives From the Leading Edge
Philip Garrou, Consultant,
June 21, 2008
ASET drives 3D Integration workshop in Tokyo
I think it was Charles Lassen (who retired from Prismark several years ago and is now...
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Vivek Bakshi, EUV Litho Inc.
Advocating More Open Communication on EUV Lithography

Vivek Bakshi, founder and president of EUV Litho Inc., explains why he started up the International Workshop on EUV Lithography, which took place in Maui in June. He also expands on recent developments in EUV, and why more research is needed.

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CMOS and Beyond: Surface Prep at Nanoscales
Now Playing: CMOS and Beyond: Surface Prep at Nanoscales
At SEMICON West 2006, Alex Braun interviews Ahmed Busnaina, director of the NSF Nanoscale Science and Engineering Center for High-Rate Nanomanufacturing at Northeastern University. Busnaina gives his perspective on the longevity of CMOS, nanotechnology, and surface preparation at nanoscales.
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Technical Articles

    Choosing the Right Thermal Interface Material
David Hirschi, Dow Corning Electronics and Advanced Technologies, Dow Corning Corp., Midland, Mich., 06/01/2008
 Specifying the right thermal interface material (TIM) requires an understanding of how interdependent elements of a TIM formulation work together and when specific considerations take priority....

    Assessing Component Damage, Failure Risk
Ray Thomas, Sonoscan, Elk Grove Village, Ill., www.sonoscan.com; Paul Melville NXP Semiconductor, Eindhoven, Netherlands, www.nxp.com, 06/01/2008
 Acoustic imaging, combined with electrical testing, provides insight into the cause of electrical failure in plastic packages....

    Electromigration-Induced Failures in Plastic Encapsulated IC Packages
William Eslinger, Boston Scientific, St. Paul, Minn., 06/01/2008
 IC failure analysis performed on potentiometer ICs revealed intermittent electrical shorts caused by a metal stringer problem....

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