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The latest news and information on semiconductor materials, including silicon wafers, compound semiconductors, low-k and high-k dielectrics, metal gates, copper, silicon on insulator (SOI), and strained silicon.
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News from Lexis Nexis July 6, 2008 SEM Enables Rapid Subnanometer 3-D Surface Imaging As critical dimensions shrink and new materials are introduced, traditional SEMs are ... More  June 27, 2008 IBM@45: eDRAM, Si! High-k, No It now appears that IBM Corp. plans to implement a high-bandwidth silicon-on-insulato... More  June 16, 2008 What's With the Name? Welcome to the debut of my very own blog, the Float Zone. Float zone wafers first cam... More May 23, 2008 RCP and the Front-End / Back-End Convergence Freescale Semiconductor Inc.’s Redistributed Chip Packaging (RCP) technology is... More » VIEW ALL BLOGS 
 Vivek Bakshi, founder and president of EUV Litho Inc., explains why he started up the International Workshop on EUV Lithography, which took place in Maui in June. He also expands on recent developments in EUV, and why more research is needed.  
 Now Playing: CMOS and Beyond: Surface Prep at Nanoscales At SEMICON West 2006, Alex Braun interviews Ahmed Busnaina, director of the NSF Nanoscale Science and Engineering Center for High-Rate Nanomanufacturing at Northeastern University. Busnaina gives his perspective on the longevity of CMOS, nanotechnology, and surface preparation at nanoscales.  More Videos >>Technical Articles
Intel’s Gargini: Semi equipment makers overestimating cost of moving to 450-mm wafersBy Ann Steffora Mutschler, Senior Editor, 06/13/2008 The move to the 450-mm wafer size has garnered an increasing amount of interest in the semiconductor manufacturing industry as many suppliers have pushed back at making the shift, arguing that there is still much to be gained in terms of efficiency from the 300-mm wafer size and noting high development costs. But with regard to the move to the 450-mm wafer size, “from a technical point of view, this is not really very difficult,” Intel Fellow Paolo Gargini says....
Self-Aligned Barrier Improves Interconnect ReliabilityH.J. Wu, J. O'loughlin, R. Shaviv, M. Sriram, K. Chattopadhyay, Y. Yu, T. Mountsier, B. van Schravendijk, S. Varadarajan, G. Dixit and R. Havemann, Novellus Systems Inc., San Jose, 05/01/2008 A new PECVD self-aligned barrier using a germanium dopant offers a simple, cost-effective means of improving electromigration resistance of copper interconnects....
Advanced Metallization Needs Integrate Copper Into MemoryNiranjan Kumar, Kevin Moraes, Murali Narasimhan and Prabu Gopalraja, Applied Materials Inc., Santa Clara, Calif., 05/01/2008 Logic interconnect technology has been driven by dual-damascene feature scaling, low-k integration and copper interconnect reliability performance requirements. With memory devices going from aluminum to copper, requirements such as gap-fill extendibility are more challenging....  View all stories
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