The latest news and information on semiconductor clean processing, including wafer cleaning; photoresist stripping; cleanrooms; environment, safety and health; and contamination control.
In Battle Against Haze, Rave Wields Rhazer David Lammers, News Editor - 07/15/2008
Rave LLC has developed a prototype haze removal system, Rhazer, which can break down haze buildup on a reticle without removing the pellicle. “We are entering a whole new market space, and we have a working prototype,” said Rave marketing manager Michael Archuletta. More
Ulvac Intros High-Throughput Asher Laura Peters, Editor-in-Chief - 07/16/2008
At SEMICON West, Ulvac introduced the Enviro Optima resist strip and residue cleaning system, which delivers 400 wph, with a modest 300 mm footprint and at the cost of $1.3M.
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iNEMI Issues Recommendations for Managing Lead-Free Solder Alloys Sally Cole Johnson, Contributing Editor - 07/10/2008
iNEMI has outlined a set of key approaches to help the electronics industry respond to the many issues and challenges emerging in the manufacturing process as a result of numerous lead-free solder alloy options.
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Yield, Surface Prep for Nano Devices Ahmed Busnaina, William Lincoln Smith Professor and Director, The NSF Nanoscale Science and Engineering Center for High-rate Nanomanufacturing and the NSF Center for Microcontamination Control - 06/01/2008 Nanoscale emerging research devices in the "beyond CMOS scaling" realm cover many applications and state variables. There have been many discussions of the characteristics, performance requirements, etc., of these devices, but the manufacture of these devices and the resulting yield has not been addressed.More
Novellus Offers Dry Strip Tools for High-Volume Memory, Advanced Logic David Lammers, News Editor - 05/19/2008
Novellus Systems announced two derivatives to its Gamma Express dry strip and clean platform: the G400, aimed at high-volume memory fabs, and the GxT, targeting the needs of advanced logic customers. The company developed a continuous RF capability that boosts throughput by continuing to ash even as wafers are moved from one station to the next.
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Haze, Still Misunderstood, Costing Industry $1B a Year Aaron Hand, Executive Editor, Electronic Media - 05/07/2008
Arguably the single largest yield detractor in the semiconductor industry, costing the industry about a billion dollars every year, micro-contamination is still very little understood or acknowledged by semiconductor fabs. Industry experts discussed the issues and various solutions in a session yesterday on time-dependent haze at ESTECH 2008.
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Applied Tackles Edge With Inflexion Polishing System David Lammers, News Editor, and Laura Peters, Editor-in-Chief - 05/07/2008
Applied Materials introduced the Inflexion edge polishing system that has an integrated wafer cleaning capability. The Inflexion tool uses abrasive tape to clean the wafer’s edge, an area that faces new contamination issues as immersion lithography pushes liquids to the edge of the wafer.
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SEZ Group Now Lam’s Spin Clean Division David Lammers, News Editor - 04/24/2008
Lam Research Corp. executives said they have created a Spin Clean Division to attack high-throughput, single-wafer cleaning opportunities. The spin clean tools acquired from the former SEZ Group will complement Lam’s linear clean tools, said Lam CEO Stephen Newberry.
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Views on News David Lammers, News Editor, Semiconductor International May 6, 2008 The Other 450 mm Shoe
The three companies openly pushing for 450 mm wafers are working on a plan to subsidi... More
Views on News David Lammers, News Editor, Semiconductor International April 9, 2008 The Donut Mystery
John Halladay, a clean process manager at Spansion’s Fab 25, brought a good mys... More
Vivek Bakshi, founder and president of EUV Litho Inc., explains why he started up the International Workshop on EUV Lithography, which took place in Maui in June. He also expands on recent developments in EUV, and why more research is needed.
Now Playing: CMOS and Beyond: Surface Prep at Nanoscales At SEMICON West 2006, Alex Braun interviews Ahmed Busnaina, director of the NSF Nanoscale Science and Engineering Center for High-Rate Nanomanufacturing at Northeastern University. Busnaina gives his perspective on the longevity of CMOS, nanotechnology, and surface preparation at nanoscales. More Videos >>
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Technical Articles
Yield, Surface Prep for Nano Devices Ahmed Busnaina, William Lincoln Smith Professor and Director, The NSF Nanoscale Science and Engineering Center for High-rate Nanomanufacturing and the NSF Center for Microcontamination Control, 06/01/2008 Nanoscale emerging research devices in the "beyond CMOS scaling" realm cover many applications and state variables. There have been many discussions of the characteristics, performance requirements, etc., of these devices, but the manufacture of these devices and the resulting yield has not been addressed....
Lower Thermal Budgets Affect Contamination Jerry Riddle, Chairman, Tiger Optics LLC, Warrington, Pa., www.tigeroptics.com, 01/01/2008 Tool builders and fab operators are constantly seeking ways to lower thermal budgets to speed throughput and use less resources, utilities and energy. However, what engineers have discovered is that with the lower-temperature process, contaminants that were not there at higher temperatures are increasingly present and remain in the process tools, pressure vessels, carriers and, in some cases, on the surface of the wafers....
Sustainable Chamber Cleaning Solutions: The Back End of the Front End Peter Lai and Paul Stockman, Linde Electronics, Murray Hill, N.J. Greg Shuttleworth, Linde Electronics, Thornton Cleveleys, UK, 01/01/2008
Sustainable and production-proven chamber cleaning solutions allow device manufacturers to deliver increased productivity and reduce environmental impact while "taking out the trash."...